File: pn_parser.xmsgs

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated   -->
<!--     by the Xilinx ISE software.  Any direct editing or        -->
<!--     changes made to this file may result in unpredictable     -->
<!--     behavior or data corruption.  It is strongly advised that -->
<!--     users do not edit the contents of this file.              -->
<!--                                                               -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.    -->

<messages>
<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file &quot;/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75.v&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file &quot;/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v&quot; into library work</arg>
</msg>

</messages>