File: add2_and_clip_reg.v

package info (click to toggle)
uhd 3.7.3-1
  • links: PTS
  • area: main
  • in suites: jessie, jessie-kfreebsd
  • size: 456,376 kB
  • ctags: 89,637
  • sloc: ansic: 51,090; cpp: 42,755; xml: 19,627; vhdl: 12,678; tcl: 5,944; python: 5,870; ada: 2,760; sh: 2,175; makefile: 615; pascal: 230; csh: 224; perl: 11
file content (25 lines) | stat: -rw-r--r-- 535 bytes parent folder | download | duplicates (14) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
 

module add2_and_clip_reg
  #(parameter WIDTH=16)
    (input clk,
     input rst,
     input [WIDTH-1:0] in1,
     input [WIDTH-1:0] in2,
     input strobe_in,
     output reg [WIDTH-1:0] sum,
     output reg strobe_out);

   wire [WIDTH-1:0] sum_int;
   
   add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int));

   always @(posedge clk)
     if(rst)
       sum <= 0;
     else if(strobe_in)
       sum <= sum_int;

   always @(posedge clk)
     strobe_out <= strobe_in;
   
endmodule // add2_and_clip_reg