File: timing.ucf

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uhd 3.7.3-1
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NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;

NET "EM_CLK" TNM_NET = "EM_CLK";
TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 18867 ps HIGH 50 %;

#constrain GPMC IO
INST "EM_D<*>" TNM = gpmc_net_out;
INST "EM_D<*>" TNM = gpmc_net;
INST "EM_A<*>" TNM = gpmc_net;
INST "EM_NCS4" TNM = gpmc_net;
INST "EM_NCS6" TNM = gpmc_net;
INST "EM_NWE" TNM = gpmc_net;
INST "EM_NOE" TNM = gpmc_net;

TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 10 ns BEFORE "EM_CLK" FALLING;
#TIMEGRP "gpmc_net_out" OFFSET = OUT 13 ns AFTER "EM_CLK" RISING; //2 clock cyc per read

#constrain interrupt lines
NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space
NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data
NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso