File: b200_clk_gen.asy

package info (click to toggle)
uhd 3.9.5-2
  • links: PTS, VCS
  • area: main
  • in suites: stretch
  • size: 107,272 kB
  • ctags: 57,231
  • sloc: cpp: 66,160; ansic: 59,349; python: 13,245; vhdl: 7,651; tcl: 2,668; sh: 1,634; makefile: 1,031; xml: 557; pascal: 230; csh: 94; asm: 20; perl: 11
file content (33 lines) | stat: -rw-r--r-- 729 bytes parent folder | download | duplicates (9) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
 
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 b200_clk_gen
RECTANGLE Normal 32 32 576 1088
LINE Normal 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName clk_in1_p
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName clk_in1_n
PINATTR Polarity IN
LINE Normal 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName reset
PINATTR Polarity IN
LINE Normal 608 80 576 80
PIN 608 80 RIGHT 36
PINATTR PinName clk_out1
PINATTR Polarity OUT
LINE Normal 608 176 576 176
PIN 608 176 RIGHT 36
PINATTR PinName clk_out2
PINATTR Polarity OUT
LINE Normal 608 272 576 272
PIN 608 272 RIGHT 36
PINATTR PinName clk_out3
PINATTR Polarity OUT
LINE Normal 608 976 576 976
PIN 608 976 RIGHT 36
PINATTR PinName locked
PINATTR Polarity OUT