1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
|
From dbda89cb5273d22883ce7554579c2049c23d2379 Mon Sep 17 00:00:00 2001
From: "A. Maitland Bottoms" <bottoms@debian.org>
Date: Thu, 1 Jul 2021 22:18:56 -0400
Subject: [PATCH 08/11] avoid doxygen misplaced alignment
The Debian package build for Doxygen and Latex breaks when using
unicode box drawing characters.
---
host/docs/calibration.dox | 4 ++--
host/docs/usrp_n3xx.dox | 17 ++++-------------
host/docs/usrp_x4xx.dox | 37 +++++--------------------------------
3 files changed, 11 insertions(+), 47 deletions(-)
--- a/host/docs/calibration.dox
+++ b/host/docs/calibration.dox
@@ -200,8 +200,8 @@
\end{pmatrix}
=
\begin{pmatrix}
-A/64+1 & 0 \\
-B/64 & 1 \\
+A/64+1 0 \\
+B/64 1 \\
\end{pmatrix}
\begin{pmatrix}
I \\
--- a/host/docs/usrp_n3xx.dox
+++ b/host/docs/usrp_n3xx.dox
@@ -1632,19 +1632,10 @@
if the master clock rate is 250 MHz, the DACs/ADCs are clocked at 500 MHz). We
perform a sample rate conversion to the master clock rate within the FPGA.
-```
- ┌───────┐ ┌──────────────┐ ┌─────────────┐ ┌──────────────┐ ┌─────┐
- │ │ │ TX │ │TX │ │ Halfband │ 2x MCR │ │
- │ ├─>│ IQ Offset ├──>│DC Offset ├─>│ Interpolator ├────────>│ DAC │
- │ │ │ Compensation │ │Compensation │ │ (47 taps) │ │ │
- │ RFNoC │ └──────────────┘ └─────────────┘ └──────────────┘ └─────┘
- │ Radio │
- │ Block │ ┌──────────────┐ ┌─────────────┐ ┌──────────────┐ ┌─────┐
- │ │ │ RX │ │RX │ │Halfband │ 2x MCR │ │
- │ │<─┤ IQ Offset │<──┤DC Offset │<─┤Decimator │<────────┤ ADC │
- │ │ │ Compensation │ │Compensation │ │(47 taps) │ │ │
- └───────┘ └──────────────┘ └─────────────┘ └──────────────┘ └─────┘
-```
+\begin{quote}
+Nicely done figure with unicode box drawing characters omitted due to errors
+in the Debian documentation building environment.
+\end{quote}
The IQ and DC offset compensation components can be controlled from the host
side using the correction APIs. The following snippet shows the control of these
--- a/host/docs/usrp_x4xx.dox
+++ b/host/docs/usrp_x4xx.dox
@@ -1172,38 +1172,11 @@
is generated digitally, within the RFSoC, and is derived from the SPLL clock.
Block diagram:
-```
- ┌────────────────────────────────────────────────────────┐
- │ Clocking Aux Board │
- │ ┌──────┐ ┌───────┐ ┌────────┐ │
- │ │GPSDO │ │ DAC │ │External│ │
- │ └─────┬┘ └─┬─────┘ └───┬────┘ │
- │ ┌v────v┐ │ ┌──────┐ │
- │ │ OCXO │ │ │ <───────┼──┐
- │ └──┬───┘ │ ┌───┐ │ MUX <───────┼─┐│
- │ │ │ │ │ └──┬───┘ │ ││
- │ ┌────v──────────────v───v─┐ │ ┌───────v───┐ │ ││
- │ │ │ └─┤eCPRI PLL │ │ ││
- │ └┐ MUX ┌┘ │LMK05318 │ │ ││
- │ └─┐ ┌─┘ │ │ │ ││
- │ └─┬─────────────────┘ └──┬────────┘ │ ││
- │ │ │ │ ││
- └───────────┼───────────────────────────┼────────────────┘ ││
- │ │ ││
- │ ┌─────────────┐ │ ││
- ┌──v──v┐ │ │ ││
- │ MUX │ │ │ ┌───── 100 MHz ││
- └──┬───┘ │ │ │ ││
- │Base Ref. Clock │ │ │ ││
- ┌───────v───────┐ │ ┌───────v──v──┐ ││
- │ Sample PLL │ └──┤Reference PLL│ ││
- │ LMK04832 │ │LMK03328 │ ││
- └──┬─────────┬──┘ └────┬────────┘ │└─ PL/Fabric Clock
- │ │ │ │
- v v v │
- Sample PLL Reference GTY Banks GTY Recovered
- Clock Clock Clock
-```
+
+\begin{quote}
+Nicely done figure with unicode box drawing characters omitted due to errors
+in the Debian documentation building environment.
+\end{quote}
Note that this section does not cover every single clock signal present on the
X410, but mainly those clock signals relevant for the operation of the RF
|
