1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module integrate
#(parameter INPUTW = 16,
parameter ACCUMW = 32,
parameter OUTPUTW = 16)
(input clk_i,
input rst_i,
input ena_i,
input dump_i,
input [INPUTW-1:0] data_i,
output reg stb_o,
output reg [OUTPUTW-1:0] integ_o
);
wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i};
reg [ACCUMW-1:0] accum;
always @(posedge clk_i)
if (rst_i | ~ena_i)
begin
accum <= 0;
integ_o <= 0;
end
else
if (dump_i)
begin
integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW];
accum <= data_ext;
end
else
accum <= accum + data_ext;
always @(posedge clk_i)
stb_o <= dump_i;
endmodule // integrate
|
