File: catgen_tb.build

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#!/bin/sh

rm -rf isim* 
rm -rf catgen_tb
rm -rf fuse*
\
#     --sourcelibdir ../../models \

vlogcomp \
    --sourcelibext .v \
    --sourcelibdir ../../coregen \
    --sourcelibdir ../../control_lib \
    --sourcelibdir . \
    --sourcelibdir $XILINX/verilog/src \
    --sourcelibdir $XILINX/verilog/src/unisims \
    --work work \
    catgen_tb.v

 
fuse -o catgen_tb catgen_tb