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# This file contains all testbenches to exlcude from the filter list discovered
# by run_testbenches.py with the Vivado simulator (xsim).
top/e31x/sim/dram_test
top/n3xx/sim/arm_to_sfp_loopback
top/n3xx/sim/aurora_loopback
top/n3xx/sim/one_gig_eth_loopback
top/n3xx/sim/ten_gig_eth_loopback
top/x300/sim/x300_pcie_int
# These testbenches only work in ModelSim
lib/axi4s_sv/axi4s_remove_bytes_tb
lib/axi4s_sv/axi4s_add_bytes_tb
lib/rfnoc/xport_sv/eth_interface_tb
lib/rfnoc/sim/eth_ipv4_interface_tb
lib/rfnoc/transport_adapters/rfnoc_ta_x4xx_eth/rfnoc_ta_x4xx_eth_tb
top/x400/ip/eth_100g_bd/lbus_tb
top/x400/rf/sim
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