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uhd 4.8.0.0%2Bds1-2
  • links: PTS, VCS
  • area: main
  • in suites: trixie
  • size: 183,172 kB
  • sloc: cpp: 279,415; python: 109,850; ansic: 103,348; vhdl: 57,230; tcl: 20,007; xml: 8,581; makefile: 2,863; sh: 2,797; pascal: 230; javascript: 120; csh: 94; asm: 20; perl: 11

Folder: x300

d .. (parent)
d d rwxr-xr-x 4,096 coregen_dsp
d d rwxr-xr-x 4,096 ip
d d rwxr-xr-x 105 sim
d d rwxr-xr-x 40 yaml_include
- - rw-r--r-- 52 .gitignore
- - rw-r--r-- 7,723 Makefile
- - rw-r--r-- 4,311 Makefile.x300.inc
- - rw-r--r-- 1,968 build_x300.tcl
- - rw-r--r-- 40,120 bus_int.v
- - rw-r--r-- 8,674 capture_ddrlvds.v
- - rw-r--r-- 141 dev_config.json
- - rw-r--r-- 3,275 gen_ddrlvds.v
- - rw-r--r-- 4,149 nirio_chdr64_adapter.v
- - rw-r--r-- 431 setupenv.sh
- - rw-r--r-- 22,358 soft_ctrl.v
- - rw-r--r-- 45,723 timing.xdc
- - rw-r--r-- 57,661 x300.v
- - rw-r--r-- 35,133 x300.xdc
- - rw-r--r-- 1,144 x300_10ge.xdc
- - rw-r--r-- 369 x300_10ge_port0.xdc
- - rw-r--r-- 369 x300_10ge_port1.xdc
- - rw-r--r-- 1,078 x300_1ge.xdc
- - rw-r--r-- 2,773 x300_HG_rfnoc_image_core.yml
- - rw-r--r-- 2,773 x300_XG_rfnoc_image_core.yml
- - rw-r--r-- 717 x300_aurora.xdc
- - rw-r--r-- 31,996 x300_core.v
- - rw-r--r-- 1,053 x300_dram.xdc
- - rw-r--r-- 12,250 x300_eth_interface.v
- - rw-r--r-- 22,300 x300_pcie_int.v
- - rw-r--r-- 18,715 x300_sfpp_io_core.v
- - rw-r--r-- 696 x300_zpu_config.vhd
- - rw-r--r-- 2,773 x310_HG_rfnoc_image_core.yml
- - rw-r--r-- 2,773 x310_XG_rfnoc_image_core.yml
- - rw-r--r-- 21,821 x3x0_base.lvbitx