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#
# Copyright 2023 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Clock definition constraints for X440 400 type images
#
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
# and RFNoC. Maximum supported master clock rate is 500 Msps @8SPC => 62.5 MHz.
# Theoretical maximum converter rate is 4.096 GSps, so really, 512 Msps @ 8SPC => 64 MHz.
set rfdc_data_clk_period 15.625
create_clock -name rfdc_r0_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
create_clock -name rfdc_r1_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
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