1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
//
// Copyright 2014 Ettus Research
// Copyright 2018 Ettus Research, a National Instruments Company
//
// SPDX-License-Identifier: GPL-3.0-or-later
//
#ifndef INCLUDED_AD9361_CLIENT_H
#define INCLUDED_AD9361_CLIENT_H
#include <memory>
namespace uhd { namespace usrp {
/*!
* Frequency band settings
*/
typedef enum { AD9361_RX_BAND0, AD9361_RX_BAND1, AD9361_TX_BAND0 } frequency_band_t;
/*!
* Clocking mode
*/
enum class clocking_mode_t { AD9361_XTAL_P_CLK_PATH, AD9361_XTAL_N_CLK_PATH };
/*!
* Digital interface specific
*/
typedef enum { AD9361_DDR_FDD_LVCMOS, AD9361_DDR_FDD_LVDS } digital_interface_mode_t;
/*!
* Interface timing
*/
typedef struct
{
uint8_t rx_clk_delay;
uint8_t rx_data_delay;
uint8_t tx_clk_delay;
uint8_t tx_data_delay;
} digital_interface_delays_t;
class ad9361_params
{
public:
typedef std::shared_ptr<ad9361_params> sptr;
virtual ~ad9361_params() {}
virtual digital_interface_delays_t get_digital_interface_timing() = 0;
virtual digital_interface_mode_t get_digital_interface_mode() = 0;
virtual clocking_mode_t get_clocking_mode() = 0;
virtual double get_band_edge(frequency_band_t band) = 0;
};
class ad9361_io
{
public:
typedef std::shared_ptr<ad9361_io> sptr;
virtual ~ad9361_io() {}
virtual uint8_t peek8(uint32_t reg) = 0;
virtual void poke8(uint32_t reg, uint8_t val) = 0;
};
}} // namespace uhd::usrp
#endif /* INCLUDED_AD9361_CLIENT_H */
|
