File: setting_reg.v

package info (click to toggle)
uhd 4.9.0.0%2Bds1-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 184,180 kB
  • sloc: cpp: 262,887; python: 112,011; ansic: 102,670; vhdl: 57,031; tcl: 19,924; xml: 8,581; makefile: 3,028; sh: 2,812; pascal: 230; javascript: 120; csh: 94; asm: 20; perl: 11
file content (23 lines) | stat: -rw-r--r-- 464 bytes parent folder | download | duplicates (11) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
 


module setting_reg
  ( input clock, input reset, input strobe, input wire [6:0] addr,
    input wire [31:0] in, output reg [31:0] out, output reg changed);
   parameter my_addr = 0;
   
   always @(posedge clock)
     if(reset)
       begin
	  out <= #1 32'd0;
	  changed <= #1 1'b0;
       end
     else
       if(strobe & (my_addr==addr))
	 begin
	    out <= #1 in;
	    changed <= #1 1'b1;
	 end
       else
	 changed <= #1 1'b0;
   
endmodule // setting_reg