File: coregen.cgp

package info (click to toggle)
uhd 4.9.0.0%2Bds1-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 184,180 kB
  • sloc: cpp: 262,887; python: 112,011; ansic: 102,670; vhdl: 57,031; tcl: 19,924; xml: 8,581; makefile: 3,028; sh: 2,812; pascal: 230; javascript: 120; csh: 94; asm: 20; perl: 11
file content (9 lines) | stat: -rw-r--r-- 230 bytes parent folder | download | duplicates (5) 
1
2
3
4
5
6
7
8
9
 
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx150
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg484
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false