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vbs 1.4.0-9
  • links: PTS
  • area: main
  • in suites: etch, etch-m68k
  • size: 2,200 kB
  • ctags: 4,401
  • sloc: cpp: 17,648; yacc: 1,880; ansic: 884; makefile: 419; sh: 375; lex: 345
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Source: vbs
Section: electronics
Priority: optional
Maintainer: Debian QA Group <packages@qa.debian.org>
Build-Depends: flex, bison, debhelper (>= 4.0.0)
Standards-Version: 3.6.1.0

Package: vbs
Architecture: any
Depends: ${shlibs:Depends}, ${misc:Depends}
Description: Verilog Behavioral Simulation
 Verilog is a Hardware Description Language used mostly for digital
 circuit design and simulation. This program is a simple
 implementation of a Verilog simulator. VBS tries to implement all of
 the Verilog behavioral constructs that are synthesizable, but still
 allow complex test vectors for simulation.