1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// parameters for array sizes
localparam WA = 4;
localparam WB = 6;
localparam WC = 8;
// 2D packed arrays
logic [WA-1:0] [WB-1:0] [WC-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] [0:WC-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
integer slc = 0; // slice type
integer dim = 0; // dimension
integer wdt = 0; // width
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin
$write("*-* All Finished *-*\n");
$finish;
end
// calculation of dimention sizes
always @ (posedge clk)
begin
// slicing tipe counter
case (cnt[3:2])
2'd0 : begin slc <= 0; end // full array
2'd1 : begin slc <= 1; end // half array
2'd2 : begin slc <= 2; end // single array element
default: begin slc <= 0; end
endcase
// dimmension counter
case (cnt[1:0])
2'd0 : begin dim <= 1; wdt = (slc==1) ? WA/2 : (slc==2) ? 1 : WA; end
2'd1 : begin dim <= 2; wdt = WB; end
2'd2 : begin dim <= 3; wdt = WC; end
default: begin dim <= 0; wdt = 0; end
endcase
end
always @ (posedge clk)
if (cnt[30:4]==1) begin
// big endian
if (cnt[3:2]==0) begin
// full array
if ($dimensions (array_bg) != 3) $stop;
if ($bits (array_bg) != WA*WB*WC) $stop;
if ((dim>=1)&&(dim<=3)) begin
if ($left (array_bg, dim) != wdt-1) $stop;
if ($right (array_bg, dim) != 0 ) $stop;
if ($low (array_bg, dim) != 0 ) $stop;
if ($high (array_bg, dim) != wdt-1) $stop;
if ($increment (array_bg, dim) != 1 ) $stop;
if ($size (array_bg, dim) != wdt ) $stop;
end
end else if (cnt[3:2]==1) begin
// half array
if ($dimensions (array_bg[WA/2-1:0]) != 3) $stop;
if ($bits (array_bg[WA/2-1:0]) != WA/2*WB*WC) $stop;
if ((dim>=1)&&(dim<=3)) begin
if ($left (array_bg[WA/2-1:0], dim) != wdt-1) $stop;
if ($right (array_bg[WA/2-1:0], dim) != 0 ) $stop;
if ($low (array_bg[WA/2-1:0], dim) != 0 ) $stop;
if ($high (array_bg[WA/2-1:0], dim) != wdt-1) $stop;
if ($increment (array_bg[WA/2-1:0], dim) != 1 ) $stop;
if ($size (array_bg[WA/2-1:0], dim) != wdt ) $stop;
end
end else if (cnt[3:2]==2) begin
// single array element
if ($dimensions (array_bg[0]) != 2) $stop;
if ($bits (array_bg[0]) != WB*WC) $stop;
if ((dim>=2)&&(dim<=3)) begin
if ($left (array_bg[0], dim-1) != wdt-1) $stop;
if ($right (array_bg[0], dim-1) != 0 ) $stop;
if ($low (array_bg[0], dim-1) != 0 ) $stop;
if ($high (array_bg[0], dim-1) != wdt-1) $stop;
if ($increment (array_bg[0], dim-1) != 1 ) $stop;
if ($size (array_bg[0], dim-1) != wdt ) $stop;
end
end
end else if (cnt[30:4]==2) begin
// little endian
if (cnt[3:2]==0) begin
// full array
if ($dimensions (array_lt) != 3) $stop;
if ($bits (array_lt) != WA*WB*WC) $stop;
if ((dim>=1)&&(dim<=3)) begin
if ($left (array_lt, dim) != 0 ) $stop;
if ($right (array_lt, dim) != wdt-1) $stop;
if ($low (array_lt, dim) != 0 ) $stop;
if ($high (array_lt, dim) != wdt-1) $stop;
if ($increment (array_lt, dim) != -1 ) $stop;
if ($size (array_lt, dim) != wdt ) $stop;
end
end else if (cnt[3:2]==1) begin
// half array
if ($dimensions (array_lt[0:WA/2-1]) != 3) $stop;
if ($bits (array_lt[0:WA/2-1]) != WA/2*WB*WC) $stop;
if ((dim>=1)&&(dim<=3)) begin
if ($left (array_lt[0:WA/2-1], dim) != 0 ) $stop;
if ($right (array_lt[0:WA/2-1], dim) != wdt-1) $stop;
if ($low (array_lt[0:WA/2-1], dim) != 0 ) $stop;
if ($high (array_lt[0:WA/2-1], dim) != wdt-1) $stop;
if ($increment (array_lt[0:WA/2-1], dim) != -1 ) $stop;
if ($size (array_lt[0:WA/2-1], dim) != wdt ) $stop;
end
end else if (cnt[3:2]==2) begin
// single array element
if ($dimensions (array_lt[0]) != 2) $stop;
if ($bits (array_lt[0]) != WB*WC) $stop;
if ((dim>=2)&&(dim<=3)) begin
if ($left (array_lt[0], dim-1) != 0 ) $stop;
if ($right (array_lt[0], dim-1) != wdt-1) $stop;
if ($low (array_lt[0], dim-1) != 0 ) $stop;
if ($high (array_lt[0], dim-1) != wdt-1) $stop;
if ($increment (array_lt[0], dim-1) != -1 ) $stop;
if ($size (array_lt[0], dim-1) != wdt ) $stop;
end
end
end
endmodule
|
