File: t_func_bad_width.v

package info (click to toggle)
verilator 3.833-1
  • links: PTS, VCS
  • area: main
  • in suites: wheezy
  • size: 10,196 kB
  • sloc: cpp: 49,566; perl: 7,111; yacc: 2,221; lex: 1,702; makefile: 651; sh: 175
file content (22 lines) | stat: -rw-r--r-- 428 bytes parent folder | download | duplicates (5) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.

module t;

   reg [3:0] out;
   reg [38:0] in;
   initial begin
      in = 39'h0;
      out = MUX (in);
      $write("bad widths %x", out);
   end

   function [31:0] MUX;
      input [39:0] XX ;
      begin
         MUX = XX[39:8];
      end
   endfunction
endmodule