File: t_gen_var_bad.v

package info (click to toggle)
verilator 3.864-1
  • links: PTS, VCS
  • area: main
  • in suites: jessie, jessie-kfreebsd
  • size: 12,272 kB
  • ctags: 19,637
  • sloc: cpp: 57,401; perl: 8,764; yacc: 2,559; lex: 1,727; makefile: 658; sh: 175
file content (12 lines) | stat: -rw-r--r-- 291 bytes parent folder | download | duplicates (4) 
1
2
3
4
5
6
7
8
9
10
11
12
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.

module t;
   integer i;
   generate
      for (i=0; i<3; i=i+1) begin	// Bad: i is not a genvar
      end
   endgenerate
endmodule