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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] time64;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
end
else if (cyc<10) begin
end
else if (cyc<90) begin
time64 = $time;
if ($stime != time64[31:0]) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
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