1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jue Xu.
// bug630
module t ( clk, out );
input clk;
output out;
reg a;
reg b;
typedef struct packed {
logic config_a;
logic config_b;
} param_t;
// verilator lint_off UNOPTFLAT
param_t conf [1:2] ;
// verilator lint_on UNOPTFLAT
always @ (posedge clk) begin
conf[2].config_b <= a;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge conf[2].config_b) begin
a = conf[2].config_a;
end
endmodule
|
