File: t_castdyn.v

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verilator 4.038-1
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t (/*AUTOARG*/);
   int i;
   int a;
   int b;
   initial begin
      i = $cast(a, b);
      if (i != 1) $stop;
      $cast(a, b);
      $write("*-* All Finished *-*\n");
      $finish;
   end
endmodule