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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Driss Hafdi.
// SPDX-License-Identifier: CC0-1.0
interface Foo();
logic quux;
endinterface
module Bar();
always_comb foo.quux = '0;
endmodule
module Baz();
Foo foo();
Bar bar();
endmodule
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
Baz baz();
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
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