1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
%Warning-IMPERFECTSCH: t/t_order_clkinst.v:18:16: Imperfect scheduling of variable: 't.c1_start'
18 | reg c1_start; initial c1_start = 0;
| ^~~~~~~~
... Use "/* verilator lint_off IMPERFECTSCH */" and lint_on around source to disable this message.
%Warning-IMPERFECTSCH: t/t_order_clkinst.v:19:16: Imperfect scheduling of variable: 't.c1_count'
19 | wire [31:0] c1_count;
| ^~~~~~~~
%Warning-IMPERFECTSCH: t/t_order_clkinst.v:23:16: Imperfect scheduling of variable: 't.s2_count'
23 | wire [31:0] s2_count;
| ^~~~~~~~
%Warning-IMPERFECTSCH: t/t_order_clkinst.v:27:16: Imperfect scheduling of variable: 't.c3_count'
27 | wire [31:0] c3_count;
| ^~~~~~~~
%Warning-IMPERFECTSCH: t/t_order_clkinst.v:71:28: Imperfect scheduling of variable: 't.c1.runner'
71 | reg [31:0] runnerm1, runner; initial runner = 0;
| ^~~~~~
%Warning-IMPERFECTSCH: t/t_order_clkinst.v:100:28: Imperfect scheduling of variable: 't.s2.runner'
100 | reg [31:0] runnerm1, runner; initial runner = 0;
| ^~~~~~
%Warning-IMPERFECTSCH: t/t_order_clkinst.v:71:28: Imperfect scheduling of variable: 't.c3.runner'
71 | reg [31:0] runnerm1, runner; initial runner = 0;
| ^~~~~~
%Error: Exiting due to
|
