File: t_past_bad.v

package info (click to toggle)
verilator 4.038-1
  • links: PTS, VCS
  • area: main
  • in suites: bullseye
  • size: 29,596 kB
  • sloc: cpp: 90,585; perl: 15,101; ansic: 8,573; yacc: 3,626; lex: 1,616; makefile: 1,101; sh: 175; python: 145
file content (15 lines) | stat: -rw-r--r-- 416 bytes parent folder | download 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2018 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t (d, clk);
   input d;
   input clk;

   always @ (posedge clk) begin
      if ($past(d, 0)) $stop;  // IEEE 16.9.3 must be >- 0
      if ($past(d, 10000)) $stop;  // TICKCOUNT
   end
endmodule