`line 1 "t/t_preproc.v" 1
// DESCRIPTION: Verilator: Verilog Test module 
// This file ONLY is placed under the Creative Commons Public Domain, for 
// any use, without warranty, 2000-2011 by Wilson Snyder. 
// SPDX-License-Identifier: CC0-1.0 

`line 6 "t/t_preproc.v" 0
//=========================================================================== 
// Includes 
 
`line 8 "t/t_preproc.v" 0
`line 1 "t/t_preproc_inc2.vh" 1
// DESCRIPTION: Verilog::Preproc: Example source code 
`line 2 "t/t_preproc_inc2.vh" 0
// This file ONLY is placed under the Creative Commons Public Domain, for 
// any use, without warranty, 2000-2007 by Wilson Snyder. 
// SPDX-License-Identifier: CC0-1.0 
At file "t/t_preproc_inc2.vh"  line 5
 
 
`line 7 "t/t_preproc_inc2.vh" 0
`line 1 "t/t_preproc_inc3.vh" 1
`line 2 "inc3_a_filename_from_line_directive" 0
// DESCRIPTION: Verilog::Preproc: Example source code 
// This file ONLY is placed under the Creative Commons Public Domain, for 
// any use, without warranty, 2000-2007 by Wilson Snyder. 
// SPDX-License-Identifier: CC0-1.0 

`line 7 "inc3_a_filename_from_line_directive" 0
 
  
  
  // FOO 
  At file "inc3_a_filename_from_line_directive"  line 11

`line 13 "inc3_a_filename_from_line_directive" 0
   
 // guard 

`line 16 "inc3_a_filename_from_line_directive" 0
 
  


`line 20 "inc3_a_filename_from_line_directive" 2
`line 7 "t/t_preproc_inc2.vh" 0


`line 9 "t/t_preproc_inc2.vh" 2
`line 8 "t/t_preproc.v" 0


`line 10 "t/t_preproc.v" 0
//=========================================================================== 
// Comments 

`line 13 "t/t_preproc.v" 0
/* verilator pass_thru comment */ 

`line 15 "t/t_preproc.v" 0
// verilator pass_thru_comment2 

`line 17 "t/t_preproc.v" 0
//=========================================================================== 
// Defines 

`line 20 "t/t_preproc.v" 0
 
 
// DEF_A0 set by command line 
   wire [3:0] q = {
		     1'b1    ,
		       1'b0  ,
		     1'b1    ,
		     1'b1   
		   };

`line 30 "t/t_preproc.v" 0
text.

`line 32 "t/t_preproc.v" 0
 
 
foo /*this */  bar   /* this too */ 
foobar2 // but not 

`line 37 "t/t_preproc.v" 0
 



`line 41 "t/t_preproc.v" 0
 




`line 46 "t/t_preproc.v" 0
/*******COMMENT*****/ 
first part 
`line 47 "t/t_preproc.v" 0
  		second part 
`line 47 "t/t_preproc.v" 0
  		third part
{
`line 48 "t/t_preproc.v" 0
		       a,
`line 48 "t/t_preproc.v" 0
		       b,
`line 48 "t/t_preproc.v" 0
		       c}
Line_Preproc_Check 49

`line 51 "t/t_preproc.v" 0
//=========================================================================== 

`line 53 "t/t_preproc.v" 0
 

`line 55 "t/t_preproc.v" 0
 
 
deep deep

`line 59 "t/t_preproc.v" 0
 
 
"Inside: `nosubst"
"`nosubst"

`line 64 "t/t_preproc.v" 0
 
x y LLZZ x y
p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s



`line 70 "t/t_preproc.v" 0
firstline comma","line LLZZ firstline comma","line

`line 72 "t/t_preproc.v" 0
 
x y LLZZ "x" y  // Simulators disagree here; some substitute "a" others do not 

`line 75 "t/t_preproc.v" 0
 
(a,b)(a,b)

`line 78 "t/t_preproc.v" 0
 
$display("left side: \"right side\"")

`line 81 "t/t_preproc.v" 0
 
bar_suffix  more

`line 84 "t/t_preproc.v" 0
 


`line 86 "t/t_preproc.v" 0
	$c("Zap(\"",bug1,"\");");;

`line 87 "t/t_preproc.v" 0
	$c("Zap(\"","bug2","\");");;

`line 89 "t/t_preproc.v" 0
/* Define inside comment: `DEEPER and `WITHTICK */ 
// More commentary: `zap(bug1); `zap("bug2"); 

`line 92 "t/t_preproc.v" 0
//====================================================================== 
// display passthru 

`line 95 "t/t_preproc.v" 0
 
 
 
 
 
 
   initial begin
      //$display(`msg( \`, \`));  // Illegal 
      $display("pre thrupre thrumid thrupost post: \"right side\"");
      $display("left side: \"right side\"");
      $display("left side: \"right side\"");
      $display("left_side: \"right_side\"");
      $display("na: \"right_side\"");
      $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\"");
      $display("na: \"nana\"");
      $display("left_side right_side	// Doesn't expand: \"left_side right_side	// Doesn't expand\"");   // Results vary between simulators 
      $display(": \"\"");  // Empty 
      $display("left side: \"right side\"");
      $display("left side: \"right side\"");
      $display("standalone");

`line 116 "t/t_preproc.v" 0
      // Unspecified when the stringification has multiple lines 
 

      $display("twoline: \"first        second\"");
      //$display(`msg(left side, \ right side \ ));  // Not sure \{space} is legal. 
      $write("*-* All Finished *-*\n");
      $finish;
   end
endmodule

`line 126 "t/t_preproc.v" 0
//====================================================================== 
// rt.cpan.org bug34429 

`line 129 "t/t_preproc.v" 0
 




`line 134 "t/t_preproc.v" 0
module add1 ( input wire d1, output wire o1);
 
`line 135 "t/t_preproc.v" 0
wire  tmp_d1 = d1; 
`line 135 "t/t_preproc.v" 0
wire  tmp_o1 = tmp_d1 + 1; 
`line 135 "t/t_preproc.v" 0
assign o1 = tmp_o1 ;   // expansion is OK 
endmodule
module add2 ( input wire d2, output wire o2);
 
`line 138 "t/t_preproc.v" 0
wire  tmp_d2 = d2; 
`line 138 "t/t_preproc.v" 0
wire  tmp_o2 = tmp_d2 + 1; 
`line 138 "t/t_preproc.v" 0
assign o2 = tmp_o2 ;  // expansion is bad 
endmodule

`line 141 "t/t_preproc.v" 0
  





`line 147 "t/t_preproc.v" 0
// parameterized macro with arguments that are macros 
  
  
  

`line 152 "t/t_preproc.v" 0
   
`line 152 "t/t_preproc.v" 0
   generate for (i=0; i<(3); i=i+1) begin 
`line 152 "t/t_preproc.v" 0
      psl cover {  m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; 
`line 152 "t/t_preproc.v" 0
      psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] &  m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; 
`line 152 "t/t_preproc.v" 0
   end endgenerate	// ignorecmt 

`line 154 "t/t_preproc.v" 0
//====================================================================== 
// Quotes are legal in protected blocks.  Grr. 
module prot();
`protected
    I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
    #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
`line 160 "t/t_preproc.v" 0
`endprotected
endmodule
//" 

`line 164 "t/t_preproc.v" 0
//====================================================================== 
// macro call with define that has comma 
 
 
 
 
 
 
 

`line 174 "t/t_preproc.v" 0
begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end  more

`line 178 "t/t_preproc.v" 0
//====================================================================== 
// include of parameterized file 
 
 
`line 181 "t/t_preproc.v" 0
`line 1 "t/t_preproc_inc4.vh" 1
// DESCRIPTION: Verilog::Preproc: Example source code 
`line 2 "t/t_preproc_inc4.vh" 0
// This file ONLY is placed under the Creative Commons Public Domain, for 
// any use, without warranty, 2000-2011 by Wilson Snyder. 
// SPDX-License-Identifier: CC0-1.0 

`line 6 "t/t_preproc_inc4.vh" 0
 

`line 8 "t/t_preproc_inc4.vh" 2
`line 181 "t/t_preproc.v" 0

`line 182 "t/t_preproc.v" 0
 
  

`line 185 "t/t_preproc.v" 0
 

`line 187 "t/t_preproc.v" 0
 
  


`line 191 "t/t_preproc.v" 0
//====================================================================== 
// macro call with , in {} 

`line 194 "t/t_preproc.v" 0
 
$blah("ab,cd","e,f");
$blah(this.logfile,vec);
$blah(this.logfile,vec[1,2,3]);
$blah(this.logfile,{blah.name(), " is not foo"});

`line 200 "t/t_preproc.v" 0
//====================================================================== 
// pragma/default net type 

`line 203 "t/t_preproc.v" 0
`pragma foo = 1
`default_nettype none
`default_nettype uwire

`line 207 "t/t_preproc.v" 0
//====================================================================== 
// Ifdef 

`line 210 "t/t_preproc.v" 0
 
 
   

`line 214 "t/t_preproc.v" 0
Line_Preproc_Check 214

`line 216 "t/t_preproc.v" 0
//====================================================================== 
// bug84 

`line 219 "t/t_preproc.v" 0
 // Hello, comments MIGHT not be legal /*more,,)cmts*/ // But newlines ARE legal... who speced THAT? 


(p,q)



`line 226 "t/t_preproc.v" 0
(//Here 	      x,y   //Too) 
Line_Preproc_Check 227

`line 229 "t/t_preproc.v" 0
//====================================================================== 
// defines split arguments 

`line 232 "t/t_preproc.v" 0
 
 
 
 
beginend   // 2001 spec doesn't require two tokens, so "beginend" ok 
beginend    // 2001 spec doesn't require two tokens, so "beginend" ok 
"beginend"  // No space "beginend" 

`line 240 "t/t_preproc.v" 0
//====================================================================== 
// bug106 
 
 
  `\esc`def

`line 246 "t/t_preproc.v" 0
Not a \`define

`line 248 "t/t_preproc.v" 0
//====================================================================== 
// misparsed comma in submacro 
 
 
 
 
x,y)--bee  submacro has comma paren

`line 256 "t/t_preproc.v" 0
//====================================================================== 
// bug191 
 
$display("10 %d %d", $bits(foo), 10);

`line 261 "t/t_preproc.v" 0
//====================================================================== 
// 1800-2009 
 
    

`line 266 "t/t_preproc.v" 0
    
    

`line 269 "t/t_preproc.v" 0
//====================================================================== 
// bug202 
 











`line 283 "t/t_preproc.v" 0

`line 283 "t/t_preproc.v" 0
   							
`line 283 "t/t_preproc.v" 0
         	
`line 283 "t/t_preproc.v" 0
      
`line 283 "t/t_preproc.v" 0
					
`line 283 "t/t_preproc.v" 0
  								
`line 283 "t/t_preproc.v" 0
     					
`line 283 "t/t_preproc.v" 0
          		
`line 283 "t/t_preproc.v" 0
    							
`line 283 "t/t_preproc.v" 0
     assign a3 = ~b3 ;						
`line 283 "t/t_preproc.v" 0
  

`line 285 "t/t_preproc.v" 0
 
/* multi	\
	 line1*/ 	\
`line 287 "t/t_preproc.v" 0
 
/*multi	\
	   line2*/ 





`line 294 "t/t_preproc.v" 0

`line 294 "t/t_preproc.v" 0
   
`line 294 "t/t_preproc.v" 0
/* multi		
      line 3*/ 		
`line 294 "t/t_preproc.v" 0
   def i		


`line 296 "t/t_preproc.v" 0
//====================================================================== 

`line 298 "t/t_preproc.v" 0
 
 
 


`line 302 "t/t_preproc.v" 0
 

 



`line 308 "t/t_preproc.v" 0
1 // verilator NOT IN DEFINE (nodef) 
2 /* verilator PART OF DEFINE */  (hasdef)
3 
`line 310 "t/t_preproc.v" 0
/* verilator NOT PART
	        OF DEFINE */  (nodef)
`line 311 "t/t_preproc.v" 0
4 
`line 311 "t/t_preproc.v" 0
/* verilator PART 
	        OF DEFINE */  (nodef)
`line 312 "t/t_preproc.v" 0
5 also in  
`line 312 "t/t_preproc.v" 0
  also3  // CMT NOT (nodef) 
 

HAS a NEW 
`line 315 "t/t_preproc.v" 0
LINE

`line 317 "t/t_preproc.v" 0
//====================================================================== 

`line 319 "t/t_preproc.v" 0
 












`line 332 "t/t_preproc.v" 0
 
 

`line 335 "t/t_preproc.v" 0
EXP: clxx_scen
clxx_scen
EXP: clxx_scen
"clxx_scen"
 
EXP: do if (start("verilog/inc1.v", 25)) begin  message({"Blah-", "clx_scen", " end"}); end  while(0);

`line 341 "t/t_preproc.v" 0
   do 
`line 341 "t/t_preproc.v" 0
      /* synopsys translate_off */  
`line 341 "t/t_preproc.v" 0
  
`line 341 "t/t_preproc.v" 0
    
`line 341 "t/t_preproc.v" 0
 
`line 341 "t/t_preproc.v" 0
      if (start("t/t_preproc.v", 341)) begin 
`line 341 "t/t_preproc.v" 0
 
`line 341 "t/t_preproc.v" 0
	 message({"Blah-", "clx_scen", " end"}); 
`line 341 "t/t_preproc.v" 0
      end 
`line 341 "t/t_preproc.v" 0
      /* synopsys translate_on */  
`line 341 "t/t_preproc.v" 0
   while(0);

`line 343 "t/t_preproc.v" 0
//====================================================================== 

`line 345 "t/t_preproc.v" 0
 




`line 349 "t/t_preproc.v" 0
    
`line 349 "t/t_preproc.v" 0
    

`line 350 "t/t_preproc.v" 0
     
//`ifndef def_fooed_2  `error "No def_fooed_2" `endif 
EXP: This is fooed
This is fooed
EXP: This is fooed_2
This is fooed_2

`line 357 "t/t_preproc.v" 0
//====================================================================== 
 
np
np
//====================================================================== 
// It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution? 
 
 
 
    

`line 368 "t/t_preproc.v" 0
 
    

`line 371 "t/t_preproc.v" 0
//====================================================================== 
// Metaprogramming 
 
 
 
 
 

`line 379 "t/t_preproc.v" 0
 
 
 

`line 383 "t/t_preproc.v" 0
hello3hello3hello3
hello4hello4hello4hello4
//====================================================================== 
// Include from stringification 
 
 
 
`line 389 "t/t_preproc.v" 0
`line 1 "t/t_preproc_inc4.vh" 1
// DESCRIPTION: Verilog::Preproc: Example source code 
`line 2 "t/t_preproc_inc4.vh" 0
// This file ONLY is placed under the Creative Commons Public Domain, for 
// any use, without warranty, 2000-2011 by Wilson Snyder. 
// SPDX-License-Identifier: CC0-1.0 

`line 6 "t/t_preproc_inc4.vh" 0
 

`line 8 "t/t_preproc_inc4.vh" 2
`line 389 "t/t_preproc.v" 0

`line 390 "t/t_preproc.v" 0
   
//====================================================================== 
// Defines doing defines 
// Note the newline on the end - required to form the end of a define 
 

 
 
     
`line 398 "t/t_preproc.v" 0
 
     
     
     
Line_Preproc_Check 402
//====================================================================== 
// Quoted multiline - track line numbers, and ensure \\n gets propagated 
 

 
Line_Preproc_Check 408
"FOO \
  BAR " "arg_line1 \
  arg_line2" "FOO \
  BAR "
`line 411 "t/t_preproc.v" 0
Line_Preproc_Check 411
//====================================================================== 
// bug283 

`line 415 "t/t_preproc.v" 0
 
 
 
// EXP: abc 
 
abc
 
 
 

`line 425 "t/t_preproc.v" 0
 
 
 
EXP: sonet_frame
sonet_frame

`line 431 "t/t_preproc.v" 0
 
 
EXP: sonet_frame
sonet_frame
// This result varies between simulators 
 
 
EXP: sonet_frame
sonet_frame

`line 441 "t/t_preproc.v" 0
// The existance of non-existance of a base define can make a difference 
 
 
EXP: module zzz ; endmodule
module zzz ; endmodule
module zzz ; endmodule

`line 448 "t/t_preproc.v" 0
 
EXP: module a_b ; endmodule
module a_b ; endmodule
module a_b ; endmodule

`line 453 "t/t_preproc.v" 0
//====================================================================== 
// bug311 
integer/*NEED_SPACE*/ foo;
//====================================================================== 
// bug441 
module t;
   //----- 
   // case provided 
   // note this does NOT escape as suggested in the mail 
 
 

   initial begin : \`LEX_CAT(a[0],_assignment)  
`line 465 "t/t_preproc.v" 0
   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) ");   end
   //----- 
   // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from 
   // substituting and the \ staying in the expansion 
   // Note space after name is important so when substitute it has ending whitespace 
 

   initial begin : \a[0]_assignment_a[1] 
`line 472 "t/t_preproc.v" 0
   $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] ");   end
 
   //----- 
 
 
   // RULE: Ignoring backslash does NOT allow an additional expansion level 
   // (Because ESC gets expanded then the \ has it's normal escape meaning) 
   initial begin : \`CAT(pp,suffix)   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) ");   end
   
   //----- 
 
 

   // Similar to above; \ does not allow expansion after substitution 
   initial begin : \`CAT(ff,bb) 
`line 486 "t/t_preproc.v" 0
   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) ");   end
   
   //----- 
 

   // MUST: Unknown macro with backslash escape stays as escaped symbol name 
   initial begin : \`zzz 
`line 492 "t/t_preproc.v" 0
   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz ");   end
 
   //----- 
 
 

   // SHOULD(simulator-dependant): Known macro with backslash escape expands 
   initial begin : \`FOO 
`line 499 "t/t_preproc.v" 0
    $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO ");  end
   // SHOULD(simulator-dependant): Prefix breaks the above 
   initial begin : \xx`FOO 
`line 501 "t/t_preproc.v" 0
   $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO ");  end
   
   //----- 
   // MUST: Unknown macro not under call with backslash escape doesn't expand 
 
   initial begin : \`UNKNOWN   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN ");   end
   //----- 
   // MUST: Unknown macro not under call doesn't expand 
 
   initial begin : \`DEF_NO_EXPAND   $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND ");   end
 
   //----- 
   // bug441 derivative 
   // SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above) 
 
   initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz");
 
   //----- 
   // RULE: Because there are quotes after substituting STR, the `A does NOT expand 
 
 
   initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz");
    
   //---- 
   // bug845 
 
   initial $write("Slashed=`%s'\n", "1//2.3");
   //---- 
   // bug915 
 

   initial 
`line 532 "t/t_preproc.v" 0
       $display("%s%s","a1","b2c3\n");
endmodule

`line 535 "t/t_preproc.v" 0
//====================================================================== 
//bug1225 

`line 538 "t/t_preproc.v" 0
 
 
$display("RAM0");
$display("CPU");

`line 543 "t/t_preproc.v" 0
 
 
 
 

`line 548 "t/t_preproc.v" 0
 
XXE_FAMILY = XXE_
 
 
     $display("XXE_ is defined");


`line 555 "t/t_preproc.v" 0
 
XYE_FAMILY = XYE_
 
 
     $display("XYE_ is defined");


`line 562 "t/t_preproc.v" 0
 
XXS_FAMILY = XXS_some
 
 
     $display("XXS_some is defined");


`line 569 "t/t_preproc.v" 0
 
XYS_FAMILY = XYS_foo
 
 
     $display("XYS_foo is defined");


`line 576 "t/t_preproc.v" 0
//==== 

`line 578 "t/t_preproc.v" 0
 
  
  
  
  
     
 

`line 586 "t/t_preproc.v" 0
  
  
  
  
     
 

`line 593 "t/t_preproc.v" 0
  
  
  
  
     
 

`line 600 "t/t_preproc.v" 0
  
  
  
  
     
 

`line 607 "t/t_preproc.v" 0
  

`line 609 "t/t_preproc.v" 0
 // NEVER 

`line 611 "t/t_preproc.v" 0
//bug1227 
 
(.mySig (myInterface.pa5),

`line 615 "t/t_preproc.v" 0
//====================================================================== 
// Stringify bug 

`line 618 "t/t_preproc.v" 0
 
`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));

`line 621 "t/t_preproc.v" 0
 
 

 




`line 629 "t/t_preproc.v" 0
module pcc2_cfg;
  generate
   
`line 631 "t/t_preproc.v" 0
  covergroup a @(posedge b); 
`line 631 "t/t_preproc.v" 0
    c: coverpoint d iff ((c) === 1'b1); endgroup 
`line 631 "t/t_preproc.v" 0
      a u_a; 
`line 631 "t/t_preproc.v" 0
   initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
  endgenerate
endmodule

`line 635 "t/t_preproc.v" 0
//====================================================================== 
// IEEE mandated predefines 
  // undefineall should have no effect on these 
predef 0 0
predef 1 1
predef 2 2
predef 3 3
predef 10 10
predef 11 11
predef 20 20
predef 21 21
predef 22 22
predef 23 23
predef -2 -2
predef -1 -1
predef 0 0
predef 1 1
predef 2 2
//====================================================================== 
// After `undefineall above, for testing --dump-defines 
 

`line 657 "t/t_preproc.v" 2