1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
|
$version Generated by VerilatedVcd $end
$date Wed Jun 10 17:27:15 2020
$end
$timescale 1ps $end
$scope module top $end
$var wire 1 # clk $end
$scope module t $end
$var wire 1 # clk $end
$var wire 3 $ cyc [2:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0#
b000 $
#10
1#
b001 $
#15
0#
#20
1#
b010 $
#25
0#
#30
1#
b011 $
#35
0#
#40
1#
b100 $
#45
0#
#50
1#
b101 $
#55
0#
#60
1#
b110 $
#65
0#
#70
1#
b111 $
#75
0#
|
