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$version Generated by VerilatedVcd $end
$date Sun Mar 1 20:49:13 2020
$end
$timescale 1ps $end
$scope module topa $end
$scope module t $end
$var wire 32 3 c_trace_on [31:0] $end
$var wire 1 # clk $end
$var wire 32 + cyc [31:0] $end
$scope module sub $end
$var wire 32 ; inside_sub_a [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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b00000000000000000000000000000001 +
b00000000000000000000000000000000 3
b00000000000000000000000000000001 ;
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b00000000000000000000000000000010 +
b00000000000000000000000000000011 3
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b00000000000000000000000000000011 +
b00000000000000000000000000000100 3
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b00000000000000000000000000000100 +
b00000000000000000000000000000101 3
#35000
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#40000
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b00000000000000000000000000000101 +
b00000000000000000000000000000110 3
#45000
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b00000000000000000000000000000110 +
b00000000000000000000000000000111 3
#55000
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#60000
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b00000000000000000000000000000111 +
b00000000000000000000000000001000 3
#65000
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b00000000000000000000000000001000 +
b00000000000000000000000000001001 3
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b00000000000000000000000000001001 +
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#85000
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b00000000000000000000000000001010 +
b00000000000000000000000000001011 3
#95000
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#100000
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b00000000000000000000000000001011 +
b00000000000000000000000000001100 3
|
