1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
