File: t_waiveroutput.v

package info (click to toggle)
verilator 4.038-1
  • links: PTS, VCS
  • area: main
  • in suites: bullseye
  • size: 29,596 kB
  • sloc: cpp: 90,585; perl: 15,101; ansic: 8,573; yacc: 3,626; lex: 1,616; makefile: 1,101; sh: 175; python: 145
file content (10 lines) | stat: -rw-r--r-- 311 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
8
9
10
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t_waiveroutput;

   reg width_warn = 2'b11;  // Width warning - must be line 18
endmodule