1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
typedef enum int {
RANDOMIZED = 20
} enumed_t;
class Cls;
int pre;
rand enumed_t r;
int post;
function void pre_randomize;
if (pre != 0) $stop;
$display("%d", r);
if (r != enumed_t'(0)) $stop;
if (post != 0) $stop;
pre = 10;
endfunction
function void post_randomize;
if (pre != 10) $stop;
if (r != RANDOMIZED) $stop;
if (post != 0) $stop;
post = 30;
endfunction
endclass
module t (/*AUTOARG*/);
initial begin
Cls c;
int rand_result;
c = new;
rand_result = c.randomize();
if (rand_result != 1) $stop;
if (c.pre != 10) $stop;
if (c.r != RANDOMIZED) $stop;
if (c.post != 30) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
