File: t_var_pinsizes.vlt

package info (click to toggle)
verilator 5.006-3
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 52,732 kB
  • sloc: cpp: 113,602; perl: 18,047; ansic: 8,633; python: 4,688; yacc: 4,382; sh: 2,094; lex: 1,815; makefile: 1,119
file content (11 lines) | stat: -rw-r--r-- 324 bytes parent folder | download | duplicates (4) 
1
2
3
4
5
6
7
8
9
10
11
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Stefan Wallentowitz.
// SPDX-License-Identifier: CC0-1.0

`verilator_config

sc_bv -module "t" -var "ibv1_vlt"
sc_bv -module "*" -var "ibv16_vlt"
sc_bv -module "*" -var "obv*_vlt"