File: t_clocking_unsup1.v

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verilator 5.032-1
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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0

module t(/*AUTOARG*/
   // Inputs
   clk
   );
   input clk;

   clocking cb @(posedge clk);
       output posedge #1 a;
       output negedge #1 b;
       output edge #1 b;
   endclocking

endmodule