File: t_dfg_regularize_driver_of_sc_var.v

package info (click to toggle)
verilator 5.032-1
  • links: PTS, VCS
  • area: main
  • in suites: trixie
  • size: 93,932 kB
  • sloc: cpp: 131,288; python: 19,365; ansic: 10,234; yacc: 5,733; lex: 1,905; makefile: 1,229; sh: 489; perl: 282; fortran: 22
file content (14 lines) | stat: -rw-r--r-- 378 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module sub(input in, output out);
  assign out = in;
endmodule

module top(input clk, output out);
  logic one = '1;
  sub sub_inst(.in(one), .out(out));
endmodule