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#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.top_filename = "t_gen_genblk.v"
test.golden_filename = "t/t_gen_genblk.out"
test.sim_time = 11000
test.compile(v_flags2=["-fno-inline"])
test.execute(expect_filename=test.golden_filename)
test.passes()
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