File: t_strength_2_uneq_assign.v

package info (click to toggle)
verilator 5.032-1
  • links: PTS, VCS
  • area: main
  • in suites: trixie
  • size: 93,932 kB
  • sloc: cpp: 131,288; python: 19,365; ansic: 10,234; yacc: 5,733; lex: 1,905; makefile: 1,229; sh: 489; perl: 282; fortran: 22
file content (19 lines) | stat: -rw-r--r-- 487 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0

module t (clk);
   input clk;
   wire [5:0] a;
   assign (weak0, strong1) a = clk ? 'z : '0;
   assign (strong0, pull1) a = 6'b110001;
   initial begin
      if (a === 6'b110001) begin
         $write("*-* All Finished *-*\n");
         $finish;
      end
   end

endmodule