File: t_timing_zerodly_unsup.out

package info (click to toggle)
verilator 5.032-1
  • links: PTS, VCS
  • area: main
  • in suites: trixie
  • size: 93,932 kB
  • sloc: cpp: 131,288; python: 19,365; ansic: 10,234; yacc: 5,733; lex: 1,905; makefile: 1,229; sh: 489; perl: 282; fortran: 22
file content (3 lines) | stat: -rw-r--r-- 235 bytes parent folder | download | duplicates (2)
1
2
3
%Warning: t/t_timing_zerodly_unsup.v:22: Encountered #0 delay. #0 scheduling support is incomplete and the process will be resumed before combinational logic evaluation.
%Error: t/t_timing_zerodly_unsup.v:23: Verilog $stop
Aborting...