File: t_tri_and_eqcase.v

package info (click to toggle)
verilator 5.032-1
  • links: PTS, VCS
  • area: main
  • in suites: trixie
  • size: 93,932 kB
  • sloc: cpp: 131,288; python: 19,365; ansic: 10,234; yacc: 5,733; lex: 1,905; makefile: 1,229; sh: 489; perl: 282; fortran: 22
file content (17 lines) | stat: -rw-r--r-- 424 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0

module t (clk1, clk2);
   input wire clk1, clk2;
   logic b = 1'bz === (clk1 & clk2);

   always begin
      if (!b) begin
         $write("*-* All Finished *-*\n");
         $finish;
      end
   end
endmodule