File: t_flag_f_tsub_inc.v

package info (click to toggle)
verilator 5.032-1
  • links: PTS, VCS
  • area: main
  • in suites: trixie
  • size: 93,932 kB
  • sloc: cpp: 131,288; python: 19,365; ansic: 10,234; yacc: 5,733; lex: 1,905; makefile: 1,229; sh: 489; perl: 282; fortran: 22
file content (3 lines) | stat: -rw-r--r-- 65 bytes parent folder | download | duplicates (8)
1
2
3
// DESCRIPTION: Verilator: Verilog Test module

`define GOT_DEF5