1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
typedef class Cls;
class Cls;
integer imembera;
integer imemberb;
endclass : Cls
module t (/*AUTOARG*/);
initial begin
string a [*];
string k;
string v;
Cls x;
v = a.num("badarg");
v = a.size("badarg");
v = a.exists(); // Bad
v = a.exists(k, "bad2");
a.delete(k, "bad2");
a.sort; // Not legal on assoc
a.rsort; // Not legal on assoc
a.reverse; // Not legal on assoc
a.shuffle; // Not legal on assoc
a.first; // Not legal on wildcard
a.last; // Not legal on wildcard
a.next; // Not legal on wildcard
a.prev; // Not legal on wildcard
a.unique_index; // Not legal on wildcard
a.find_index; // Not legal on wildcard
a.find_first_index; // Not legal on wildcard
a.find_last_index; // Not legal on wildcard
a[x] = "bad";
a.bad_not_defined();
end
endmodule
|
