File: t_cover_line.vlt

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Stefan Wallentowitz.
// SPDX-License-Identifier: CC0-1.0

`verilator_config

coverage_block_off -file "t/t_cover_line.v" -lines 145
coverage_block_off -file "t/t_cover_line.v" -lines 179
coverage_block_off -module "beta" -block "block"