File: t_dfg_inline_forced.v

package info (click to toggle)
verilator 5.038-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 162,552 kB
  • sloc: cpp: 139,204; python: 20,931; ansic: 10,222; yacc: 6,000; lex: 1,925; makefile: 1,260; sh: 494; perl: 282; fortran: 22
file content (24 lines) | stat: -rw-r--r-- 495 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module top(input wire clk);

    logic [1:0][31:0] i;
    logic o;

    always @(posedge clk) begin
        force i = 64'hFFFFFFFF_FFFFFFFF;
    end

    sub sub_i(.i(i), .o(o));
endmodule

module sub (
    input  logic [63:0] i,
    output logic o
);
    assign o = |i;
endmodule