1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
int evt_recv_cnt;
int new_evt_recv_cnt;
module t();
class Foo;
event evt1;
task automatic send_evt();
fork
#10 begin ->evt1; end
begin
event new_event;
#20;
// This should cause an event merge but for now we don't support that.
evt1 = new_event;
end
#30 begin
@evt1 $display("Received a new event");
new_evt_recv_cnt++;
end
join_none
endtask
task wait_for_event();
fork begin
@evt1 $display("Received evt1");
evt_recv_cnt++;
end join_none
endtask
endclass
initial begin
Foo foo1;
foo1 = new;
evt_recv_cnt = 0;
new_evt_recv_cnt = 0;
for (int i = 0; i < 4; i++) begin
foo1.wait_for_event();
#10;
foo1.send_evt();
#90;
$display("- end of iteration -");
if (evt_recv_cnt != i + 1)
$stop;
if (new_evt_recv_cnt != i)
$stop;
end
if (evt_recv_cnt != 4)
$stop;
if (new_evt_recv_cnt != 3)
$stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
