File: t_fork_repeat.v

package info (click to toggle)
verilator 5.038-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 162,552 kB
  • sloc: cpp: 139,204; python: 20,931; ansic: 10,222; yacc: 6,000; lex: 1,925; makefile: 1,260; sh: 494; perl: 282; fortran: 22
file content (34 lines) | stat: -rw-r--r-- 669 bytes parent folder | download | duplicates (2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t(/*AUTOARG*/);
   bit clk;

   // Gen Clock
   always #10
     clk = ~clk;

   initial begin
      fork
         begin
            forever
              @(posedge clk);
         end
         begin
            repeat(10)
              @(posedge clk);
         end
         begin
            for(int i=0; i < 6; ++i)
              @(posedge clk);
         end
      join_any

      $write("*-* All Finished *-*\n");
      $finish;
   end

endmodule