1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by John Stevenson.
// SPDX-License-Identifier: CC0-1.0
typedef logic [63:0] uid_t;
typedef logic [31:0] value_t;
interface the_intf #(parameter M = 5);
logic valid;
uid_t uid;
value_t [M-1:0] values;
modport i(
output valid,
output uid,
output values
);
modport t(
input valid,
input uid,
input values
);
endinterface
module Contemplator #(
parameter IMPL = 0,
parameter M = 5,
parameter N = 1 )
(
input logic clk,
the_intf.i out [N-1:0]
);
the_intf #(.M(M)) inp[N-1:0] ();
DeepThought #(
.N ( N ))
ultimateAnswerer(
.src ( inp ),
.dst ( out ));
endmodule
module DeepThought #(
parameter N = 1 )
(
the_intf.t src[N-1:0],
the_intf.i dst[N-1:0]
);
endmodule
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam M = 5;
localparam N = 1;
the_intf #(.M(M)) out0 [N-1:0] ();
the_intf #(.M(M)) out1 [N-1:0] ();
Contemplator #(
.IMPL ( 0 ),
.M ( M ),
.N ( N ))
contemplatorOfTheZerothKind(
.clk ( clk ),
.out ( out0 ));
Contemplator #(
.IMPL ( 1 ),
.M ( M ),
.N ( N ))
contemplatorOfTheFirstKind(
.clk ( clk ),
.out ( out1 ));
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
