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%Warning-STMTDLY: t/t_net_delay.v:16:11: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
16 | always #2 clk = ~clk;
| ^
... For warning description see https://verilator.org/warn/STMTDLY?v=latest
... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
%Warning-STMTDLY: t/t_net_delay.v:22:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
22 | wire[3:0] #3 val1;
| ^
%Warning-STMTDLY: t/t_net_delay.v:23:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
23 | wire[3:0] #3 val2;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:24:14: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
24 | wire[3:0] #5 val3 = cyc;
| ^
... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
%Warning-STMTDLY: t/t_net_delay.v:25:14: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
25 | wire[3:0] #5 val4;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:26:14: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
26 | wire[3:0] #3 val5 = x, val6 = cyc;
| ^
%Warning-ASSIGNDLY: t/t_net_delay.v:29:11: Ignoring timing control on this assignment/primitive due to --no-timing
: ... note: In instance 't'
29 | assign #3 val2 = cyc;
| ^
%Warning-STMTDLY: t/t_net_delay.v:41:26: Ignoring delay on this statement due to --no-timing
: ... note: In instance 't'
41 | always @(posedge clk) #1 begin
| ^
%Error: Exiting due to
|
