File: t_sarif.v

package info (click to toggle)
verilator 5.038-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 162,552 kB
  • sloc: cpp: 139,204; python: 20,931; ansic: 10,222; yacc: 6,000; lex: 1,925; makefile: 1,260; sh: 494; perl: 282; fortran: 22
file content (22 lines) | stat: -rw-r--r-- 486 bytes parent folder | download 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
 
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t(
    input clk1,
    input clk2,
    output logic multidriven);

   wire [1:0] trunced = 5'b11111;  // Warned

   always @ (posedge clk1)
     multidriven <= '1;
   always @ (posedge clk2)
     multidriven <= '0;

endmodule

module t;  // BAD duplicate
endmodule