1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2030 by Stephen Henry.
// SPDX-License-Identifier: CC0-1.0
module t;
int fdin_bin, fdout_txt, fdout_bin;
`define STRINGIFY(x) `"x`"
`define checkh(gotv,expv) \
do if ((gotv) !== (expv)) begin\
$write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));\
end while(0)
//
//
task automatic test1; begin
for (int i = 0; i < 256; i++) begin
byte actual, expected;
expected = i[7:0];
$fscanf(fdin_bin, "%u", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%u", actual);
end
for (int i = 0; i < 256; i++) begin
shortint actual, expected;
for (int j = 0; j < 2; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%u", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%u", actual);
end
for (int i = 0; i < 256; i++) begin
int actual, expected;
for (int j = 0; j < 4; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%u", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%u", actual);
end
for (int i = 0; i < 256; i++) begin
longint actual, expected;
for (int j = 0; j < 8; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%u", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%u", actual);
end
end endtask
//
//
task automatic test2; begin
for (int i = 0; i < 256; i++) begin
byte actual, expected;
expected = i[7:0];
$fscanf(fdin_bin, "%z", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%z", actual);
end
for (int i = 0; i < 256; i++) begin
shortint actual, expected;
for (int j = 0; j < 2; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%z", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%z", actual);
end
for (int i = 0; i < 256; i++) begin
int actual, expected;
for (int j = 0; j < 4; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%z", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%z", actual);
end
for (int i = 0; i < 256; i++) begin
longint actual, expected;
for (int j = 0; j < 8; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%z", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%z", actual);
end
end endtask
initial begin : main_PROC
string filename;
filename = "t/t_sys_file_basic_uz.dat";
fdin_bin = $fopen(filename, "rb");
`ifdef IVERILOG
filename = $sformatf("%s/t_sys_file_basic_uz_test.log","obj_iv/t_sys_file_basic_uz");
`else
filename = $sformatf("%s/t_sys_file_basic_uz_test.log",`STRINGIFY(`TEST_OBJ_DIR));
`endif
fdout_txt = $fopen(filename, "w");
`ifdef IVERILOG
filename = $sformatf("%s/t_sys_file_basic_uz_test.bin","obj_iv/t_sys_file_basic_uz");
`else
filename = $sformatf("%s/t_sys_file_basic_uz_test.bin",`STRINGIFY(`TEST_OBJ_DIR));
`endif
$display(filename);
fdout_bin = $fopen(filename, "wb");
test1;
test2;
$fclose(fdin_bin);
$fclose(fdout_txt);
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end // block: main_PROC
`undef STRINGIFY
endmodule // t
|
