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$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module t $end
$var wire 32 * CLK_PERIOD [31:0] $end
$var wire 32 + CLK_HALF_PERIOD [31:0] $end
$var wire 1 # rst $end
$var wire 1 ( clk $end
$var wire 1 $ a $end
$var wire 1 ) b $end
$var wire 1 % c $end
$var wire 1 & d $end
$var event 1 ' ev $end
$upscope $end
$enddefinitions $end
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