File: t_timing_trace_fst.out

package info (click to toggle)
verilator 5.038-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 162,552 kB
  • sloc: cpp: 139,204; python: 20,931; ansic: 10,222; yacc: 6,000; lex: 1,925; makefile: 1,260; sh: 494; perl: 282; fortran: 22
file content (93 lines) | stat: -rw-r--r-- 698 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
$date
	Tue Jun 10 19:01:39 2025

$end
$version
	fstWriter
$end
$timescale
	1ps
$end
$scope module t $end
$var parameter 32 ! CLK_PERIOD [31:0] $end
$var parameter 32 " CLK_HALF_PERIOD [31:0] $end
$var logic 1 # rst $end
$var logic 1 $ clk $end
$var logic 1 % a $end
$var logic 1 & b $end
$var logic 1 ' c $end
$var logic 1 ( d $end
$var event 1 ) ev $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1)
0(
1'
1&
0%
0$
1#
b00000000000000000000000000000101 "
b00000000000000000000000000001010 !
$end
#5
1$
#10
0$
0'
1)
#15
1$
#20
0$
1)
1'
#25
1$
#30
0$
0'
1)
#35
1$
#40
0$
1)
1'
#45
1$
#50
0$
0'
1)
#55
1$
#60
0$
1)
1'
#65
1$
#70
0$
0'
1)
#75
1$
#80
0$
1)
1'
#85
1$
#90
0$
0'
1)
#95
1$
#100
0$
0&