File: t_trace_abort_fst_sc.out

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$date
	Sat Apr  5 13:56:20 2025

$end
$version
	fstWriter
$end
$timescale
	1ps
$end
$scope module top $end
$scope module t $end
$var wire 1 ! clk $end
$var logic 3 " cyc [2:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
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