File: t_trace_timing1.out

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$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module t $end
  $var wire 32 % CLOCK_CYCLE [31:0] $end
  $var wire 1 # rst $end
  $var wire 1 $ clk $end
 $upscope $end
$enddefinitions $end


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